`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:47:43 11/23/2024
// Design Name:   JK
// Module Name:   C:/CYH/ISE/6/Lab6/test01.v
// Project Name:  Lab6
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: JK
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test01;

	// Inputs
	reg cp;
	reg J;
	reg K;
	reg sD_;
	reg rD_;

	// Outputs
	wire Q;
	wire Q_;

	// Instantiate the Unit Under Test (UUT)
	JK uut (
		.cp(cp), 
		.J(J), 
		.K(K), 
		.sD_(sD_), 
		.rD_(rD_), 
		.Q(Q), 
		.Q_(Q_)
	);

	initial begin
		// Initialize Inputs
		cp = 0;
		J = 0;
		K = 0;
		sD_ = 0;
		rD_ = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#100 cp=0; sD_=0; rD_=1; J=1; K=1;
		#100 cp=1; sD_=0; rD_=1; J=1; K=1;
		
		#100 cp=0; sD_=1; rD_=0; J=1; K=1;
		#100 cp=1; sD_=1; rD_=0; J=1; K=1;
		
		
		#100 cp=0; sD_=1; rD_=0; J=1; K=1;
		
		#100 cp=0; sD_=1; rD_=1; J=1; K=0;
		#100 cp=1; sD_=1; rD_=1; J=1; K=0;
		
		#100 cp=0; sD_=1; rD_=1; J=0; K=1;
		#100 cp=1; sD_=1; rD_=1; J=0; K=1;
		
		#100 cp=0; sD_=1; rD_=1; J=1; K=1;
		#100 cp=1; sD_=1; rD_=1; J=1; K=1;
		
		#100 cp=0; sD_=1; rD_=1; J=0; K=0;
		#100 cp=1; sD_=1; rD_=1; J=0; K=0;
		
		#100 cp=0; sD_=1; rD_=1; J=1; K=1;
		#100 cp=1; sD_=1; rD_=1; J=1; K=1;
		
		#100 cp=0; sD_=1; rD_=1; J=1; K=1;
		#100 cp=1; sD_=1; rD_=1; J=1; K=1;
		
		
		
		
	end
      
endmodule

